Electrothermal Analysis of Three-Dimensional Integrated Circuits.

Transient electro-thermal simulation of a three dimensional integrated circuit (3DIC) is

reported that uses a cell-based simulation to provide a selected transistor thermal profile while

providing advantages of hierarchical simulation. Due to CPU and memory limitations, full

transistor electro-thermal simulations on a useful scale are not possible. Standard cells are

considered on a per-instance basis and modeled with electro-thermal macro-models developed

in a multi-physics simulator. Simulations are compared favorably to measurements for a token-

generating 3DIC clocking at a maximum of 1 GHz. The 3DIC, which is composed of 9 by 3

layers of repetitive frequency multipliers and dividers, was fabricated with the Massachusetts

Institute of Technology Lincoln Laboratory (MITLL) 3DIC process.